CMOS was initially favoured by engineers due to its high speed and reduced area. They were very power efficient as they dissipate nearly zero power when idle. But as the technology developed and due to increase in the transistor count per chip and high frequency clocks, power dissipation has become a major concern for CMOS in recent days.
In CMOS, there are two broad classification of power dissipation.
- Static
- Dynamic
Ptotal = Pstatic + Pdynamic
Static Dissipation
Static dissipation, commonly called as Leakage, constitutes of,
- Sub-threshold conduction through OFF transistors
- Tunneling through Gateoxide
- Leakage through revere biased diodes
Subthreshold conduction
A CMOS circuit typically consists of PMOS and NMOS within. For example, a CMOS inverter consists of one PMOS transistor and one NMOS transistor. If input to the inverter is 1, PMOS turns OFF and NMOS turns ON, clamping the output to 0 and vice versa for input 0. Hence depending on input, one of the transistor in CMOS is always OFF. Ideally there shouldn't be any power consumption due to these OFF transistors. But this is not the case in reality. Even OFF transistors consume certain amount of power. Less the threshold voltage of transistor, more the power consumption. Since it primarily depends on the threshold voltage, it is named as sub-threshold conduction. As the technology shrinked and threshold voltage also reduced drastically, sub-threshold conduction is becoming notably high threat.
Tunneling
Gate Oxide is a thin layer which acts as an insulator between gate (Poly) and Substrate. Usually SiO2 is used as the material for gate oxide, because of high insulating capability. But still there is a probability for electrons to tunnel (pass) through the gate oxide and initiate conduction. This results in unintentional power consumption. The tunneling probability reduces as the gate oxide thickness increases.
Leakage through reverse biased diodes
Basically transistor is made of p and n materials, which means there exists a diode between p and n junctions. In the figure shown below, there exists diodes between each n wells and p-substrate. There are chances that forms a reverse biased leakage current flowing through the pn junction diode causing undesired power consumption. In modern processes, diode leakage is much smaller compared to sub-threshold and tunneling leakage.
Dynamic Dissipation
Dynamic dissipation constitutes of,
- Charging and discharging of load capacitance
- Short circuit current
Charging and discharging of load Capacitance
This is the primary dissipation component of dynamic dissipation. Lets assume an inverter output Y is connected to an NAND input pin A. Load for the inverter pin Y is the total capacitance of NAND input pin A and net (metal) connecting between these two pins.
Load capacitance of Y = Net capacitance + Input pin capacitance of A
This means that, for the output of inverter to reach the input of NAND, it should either charge or discharge the load capacitance depending on the value at Y (0 or 1). This process of charging and discharging constitutes major amount of power consumption.
Short Circuit Current
It takes a certain amount of time to charge or discharge the load capacitance by the input pin (Slew or Transition time). During this time, both the transistors (PMOS and NMOS) of a CMOS will be ON. For example, in an inverter lets assume that the initial input was 0 and then we change it to 1. For input 0, PMOS will be ON (Vdd) and NMOS will be OFF (Gnd). When the input changes to 1, PMOS will discharge to become OFF and NMOS will start charging to become ON. This is explained in detail in the below figure.
You can see that both the transistors are ON for a short duration Ton. Hence during this time, both transistors draw current. This current is termed as Short circuit current.
The charging time is called as Rise time (Tr) whereas discharging time is called as Fall time (Tf). In general charging time (Tr) is always more than the discharging time (Tf). Hence to reduce this short circuit current, a transistor with less rise time and fall time is always preferred.
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