Physical Design Flow - Stage 1 - Sanity Checks

Whenever you go for a shopping, you will buy a product only after making sure that there is no defect/malfunction, right? In simple terms, that is sanity check - making sure whatever you get is in good shape/condition. 

As a physical design engineer, you will be getting multiple inputs from multiple teams. So you need to make sure that the inputs you are getting is complete and good enough to proceed with. 

Need for sanity checks

Mandatory inputs for PD flow are,

• Gate level netlist (.v)
• Physical Libraries (.lef or .mw)
• Logic and Timing Libraries (.lib or .db)
• Timing Constraints (.sdc)

Gate Level Netlist is given by a Synthesis team. If you own the synthesis part, then your input will be RTL netlist from an RTL engineer.

Physical Libraries is given by IP-vendor or Foundry

Timing Libraries is also given by IP-vendor or Foundry

Timing Constraints is given by the synthesis team. If you own the synthesis part, then you will be writing the sdc's (Synopsys Design Constraints). 

Now, our first job in PD flow is to make sure these four inputs are complete and not erroneous. We have a few commands [varies according to the tool used] to check these. Lets see about those commands in detail.

Implementation

Synopsys Flow

In ICC, following are the sanity check commands,

• check_design
• check_library
• check_timing

check_design checks for certain problems such as unloaded input ports or undriven output ports, nets without loads or drivers or with multiple drivers, cells or designs without inputs or outputs, mismatched pin counts between an instance and its reference, tristate buses with non-tristate drivers, wire loops (timing loops with no cells in them) across hierarchies, and so forth.
check_library checks the consistency between logic and physical libraries. This means it will check whether each cell [AND, OR, etc] described in the design netlist has its corresponding physical library and logic/timing information defined in a logic/timing library.

check_timing checks whether all the paths in a design are constrained and consistency prevails between the constraints. In simple terms, it checks whether all ports has its corresponding input/output delays specified and clock definition exists for clock pins of all flops. 

Cadence Flow

In EDI/Innovus, following are the sanity check commands,

• checkDesign [-netlist | -physicalLibrary | -timingLibrary]
• check_timing
• checkUnique

check_design -netlist checks for multi driven nets, floating nets/pins, empty modules, assign statements.

check_design -physicalLibrary checks physical libraries and reports whether all cells have its corresponding LEF views.

check_design -timingLibrary checks whether the all cells used in the design have its corresponding timing library.

check_timing checks whether all the paths in a design are constrained and consistency prevails between the constraints.
checkUnique checks whether the netlist is unique - multiple instantiation of the same module inside a netlist.

Example Reports:

check_design

check_timing