Major Domains in VLSI

This post is regarding an overview of different domains available in VLSI field on the career front. For those who want to start their career in VLSI, this post might be useful.

Following are the major domains in VLSI design,

• Analog Layout Design
• RTL Design
• Design Verification
• DFT
• Physical Design [Including Synthesis and STA]
• Physical Verification
• Post Silicon Validation

Lets see a brief description of each of these domains.

Analog Layout

   Analog layout deals with giving a physical view to a basic logic/circuit. Analog Layout Engineers will be manually designing the physical layout, starting from logic gates (NAND, NOR, etc) to complex PLL's and IO's, based on the foundry requirements and fabrication processes. In simple terms, they will be creating the basic building blocks for a bigger design.

   Each process technology node (example - 14nm or 28nm) requires new layout design for the same circuit. Hence Analog Layout Engineers have to be always updated with latest process technologies and techniques. This domain also requires in-depth knowledge of electronics and cmos.

Tools used - Cadence Virtuoso

Example of a layout using Industry standard Cadence Virtuoso Tool

RTL design

    RTL design [RTL - Register Transfer Level], commonly called as Front End Design, brings life to an idea through a Hardware Description Language such as Verilog or VHDL code. RTL Design Engineers create codes to realize a logic/functionality which is the sole requirement of a customer. Engineers should be innovative in their coding styles and expert in logic understanding and digital design.

Example of a Verilog code is given below, 

Design Verification

    Design Verification verifies whether the written RTL code performs the expected functionality. The main job of a Design verification Engineer is to write a verilog code (different from RTL code) called as "Test Bench" which contains the sample inputs for the actual RTL code. The Test bench and the RTL code is given to a simulation tool which simulates the functionality of the RTL code for the given sample inputs from test bench. The output of the simulation tool is then compared with the expected output and thus functionality can be verified. Expertise required is same as that required for an RTL design Engineer.

Simulation tools - ModelSim, VCS

Example of a test bench for an AND logic and its corresponding simulation result is shown below.

DFT - Design For Testability

    This domain focuses on adding a test architecture within the chip which helps in testability after it is manufactured. This is to make sure that the manufactured chip is functionally defect free. One of the basic DFT architecture is scan chain, in which all the registers inside a design are connected together to form of a chain [one after the other]. In simple terms, When you give a 0 or 1 to the scan chain input, after passing through all the registers you should eventually get output same as that of input, since the function of a register is only to store the given value. This method is used to check stuck at 0 and 1 faults. Few other examples of DFT architectures include BIST, ATPG, etc.

Tools used - TetraMax for ATPG

Physical Design [Including Synthesis and STA]

    This domain is popularly known as Back-End design. Physical Design Engineer owns the responsibility in converting an RTL code into a physical layout. In RTL design and Design verification stages, we will be concentrating on realising the actual functionality of the design, whereas in this stage we will be concentrating on physical aspects such as the size of the chip, metal layers to be used, congestion, meeting timing parameters and many more.

Tools used- Synopsys ICC, ICC2, Cadence Innovus

Physical Verification

    Physical Verification verifies whether the IC layout designed using EDA tools can be manufactured without any defects to realise the expected functionality. Physical verification actually improves the yield in IC manufacturing. Major physical verification checks are,

Design Rule Check (DRC) - Checks whether the design meets all the foundry related rule deck

Layout Versus Schematic (LVS) - Checks whether the designed layout has the same functionality as that of  the golden RTL code

Apart from DRC and LVS, you have Antenna checks, Double Patterning checks (especially for nodes below 16nm), Electrical Rule Checking, etc

Tools used - Mentor Graphics Calibre

Post-Silicon validation

   Post silicon validation is the final verification stage in which the manufactured IC is implemented in a test board and checked for functional correctness by using a predefined test stimulus. This is more of a hardware job which requires industry standard hardware tools and appropriate lab facilities.

If there any discrepancies in the explanation, please comment.

Image Source - Google