VLSI Physical Design Interview Questions

In this post, I am not going to spam you with usual interview questions. I have given questions, only which i felt was a little tricky or out of the usual ones during my interviews.

1. How do you qualify your floorplan is good?
2. What is Congestion and what are the ways to reduce congestion?
3. What is max_trans constraint? Say your design's timing is fine but you have at least one (or more) max-tran violation. Is it ok to tape out the design without clearing the max_transition violation? 
4. How do you arrive at max_transition constraint value?
5. What is max_fanout constraint? Say your design's timing is fine but you have at least one (or more) max_fanout violation. Is it ok to tape out the design without clearing the max_fanout violation?
6. What is latch up effect and what is the technique used to reduce the effect?
7. What is the difference between 9T and 12T cells in terms of area, performance and power?
8. Difference between different VT cells (LVT, SVT,HVT,etc) and how do they differ internally?
9. What is a multi cycle path? For a multi cycle path of 4 cycles, on which cycle edge do setup and hold check occur?
10. What is the difference between a clock buffer and a normal buffer?
11. Did you use clock buffer or clock inverter in your design and why?
12. Say after CTS, your skew target is met but your latency is more than the expected, is it ok to proceed? Justify your answer.
13. What are the different physical only cells and why do we need them?
14. What is the difference between graph based and path based analysis? 
15. What is ERC?
16. Which check is frequency independant, setup or hold? Have you heard of frequency dependant hold check?
17. What is an Isolation cell? What are the types of isolation cell and how you choose which cell to add?
18. Explain IR drop analysis and in which scenario (best,typ,worst) you will run IR drop analysis? Justify your answer.
19. In which scenario (best,typ,worst) you will run power optimization. Justify your answer.
20. What are min-density rules and why do we need them?
21. How do you fix setup and hold violations in scan mode?
22. In StarRC, what is "Un-annotated Nets" ? Is it ok to proceed with the SPEF that contains un-annotated nets?

More questions and Answers will be posted soon..